Noise Modeling and Optimization of a 130-nm High-Rate Readout Integrated Circuit With Auto-Reset Feedback for Deep-Silicon-Based Energy-Resolved Photon-Counting CT

Deep-silicon detectors emerge as a prime solution for next-generation X-ray photon-counting CT imaging due to their exceptional high-energy compatibility (up to 100 keV), sub-nanosecond temporal resolution, and superior radiation hardness. Similar to silicon microstrip readout, these detectors require multi-channel front-end readout application-specific integrated circuits (ASICs) to process and count charge signals from microstrips. Leveraging existing X-ray tube technology, the low energy deposition per detector unit (as low as 2 keV) necessitates ultra-low-noise analog front-ends with ENC2. Conventional noise models fail to optimize such high-flux circuits. In this paper, a physics-based ENC model is derived for high-count-rate automatic feedback reset architecture, revealing fundamental trade-offs between noise, speed, and power. Guided by this model, we propose a systematic low-noise design methodology and implement a 64-channel ASIC in 130-nm CMOS. The error between circuit-level simulation results and modeling predictions is within 10%. Experimental results demonstrate a maximum count rate of 10.2 Mcps and the ENC is 250 el.rms with a 12.4 el/pF slope at 2.5 mW/channel. Simulations and measurements jointly confirm the model’s accuracy in guiding low-noise design for high-count-rate photon-counting ASICs.