Effect of the Anti-Punchthrough Implant on the Total Ionizing Dose Response of Planar Silicon n-MOSFETs

The aggressive scaling of CMOS devices has led to a decreased sensitivity of the gate oxide to Total Ionizing Dose (TID) effects. Currently, the TID tolerance of scaled transistors is primarily related to charge trapping in other thick isolation oxides, such as Shallow Trench Isolations (STI). Moreover, to mitigate the short-channel effects, including the threshold voltage roll-off, drain-induced barrier lowering (DIBL), and punchthrough, modern technologies include non-uniform bulk doping profiles determined by halos and anti-punchthrough (APT) implants. These implants add complexity to the understanding of TID effects related to the charge trapping in the STI. In this work, we combined experimental results with TCAD simulations to highlight the key role of the APT implant in influencing the TID-sensitivity of planar MOSFETs. The results demonstrate that variation in the APT doping, depth, and width significantly impacts the off-leakage current, which is a major concern in irradiated n-MOSFETs. The highest TID tolerance is achieved in transistors designed with the APT implantation depth close to the drain/source extension depth, while the TID degradation of threshold voltage and transconductance is slightly affected by the APT. Notably, these changes in APT implantation parameters may not be evident in the pre-radiation characteristics but can substantially affect the TID resilience. As a result, transistors with different APT implantation profiles exhibit similar pre-rad ID-VGSbut diverge in their TID sensitivities.