Impact of Silicon Thinning on Single-Event Upsets in 28-nm Bulk CMOS 6T SRAMs

This work investigates how thinning the Si substrate alters the single event upset (SEU) response of 6T SRAM cells fab-ricated in a bulk 28 nm CMOS process technology. Previously published results on bulk 0.6 μm CMOS process SRAM cells showed that thinning provides significant hardening against SEU. Laser raster-scan data, heavy-ion data, and TCAD SEU simula-tions are all in qualitative agreement that thinning the 28 nm pro-cess SRAM cells increases SEU susceptibility. TCAD analysis demonstrates that thinning triggers the parasitic bipolar junction transistor (BJT) mechanism prompted by the ion-strike and that this mechanism is enhanced by substate thinning. Thinning in-creases the resistance at the region connecting the base of the built-in parasitic BJT to the body electrode. Therefore, the potential in the base, caused by ion-generated hole transport out of the body region is higher in the thinner case, enabling a hole current out of the NFET via the body electrode. This higher potential in the par-asitic BJT “base” region enables greater forward-biasing at the source(emitter)/body(base) junction. Thus, the thinner case has more back-injected electrons from the emitter when compared to the thicker case. These excess electrons lead to greater charge col-lection at the sensitive drain nodes of the SRAM. The simulated linear energy transfer thresholds (LETTH) are slightly less for the thinner parts which correlates to laser and heavy ion data.