An FPGA-Based Single-Slope ADC With an Improved ERBW of 23 MHz

Single-slope analog-to-digital converter (ADC) is relatively suitable to be implemented on field-programmable gate array (FPGA) platform for signal digitization of particle detectors. Although existing designs have made significant progress, the simplicity of implementation and the best performance that can be achieved have not yet been fully explored. This paper proposes an FPGA-based single-slope ADC implementation with two unique characteristics. The first is that by converting the sampling point into two consecutive narrow pulse width measurements, the sampling value can be accurately obtained by one time-to-digital converter (TDC) while keeping the ADC sampling clock and TDC measurement clock completely independent. The second is that by reconstructing the sampling value at the sampling moment through linear interpolation, the non-uniform sampling error can be removed to obtain the maximum possible effective resolution bandwidth (ERBW). The proposed ADC was implemented on a Xilinx Kintex UltraScale+ FPGA for performance evaluation, which can achieve an effective number of bits (ENOB) of 6.51 with an ERBW of 23 MHz at an input range of 120 mV - 1790 mV. By comparing with the complex implementation designed only for best performance, the proposed ADC can not only ensure the versatility and simplicity of ADC implementation, but also achieve the best performance that this type of ADC should have.