Reliable AI Accelerator Design Using Multiple Fault-Tolerance Techniques on SRAM-Based APSoCs

As Convolutional Neural Networks (CNNs) implemented on All Programmable System on Chips (APSoCs) are increasingly adopted in space mission-critical systems due to their flexibility and parallelism, selecting a fault-tolerant design that balances reliability, area, and power is essential to address radiation-induced faults and resource constraints. However, the literature offers limited exploration of the combined use of multiple fault-tolerance techniques within a single AI accelerator, making it difficult to identify the most effective strategies. To address this, we propose a generalizable design flow and apply it to the ZynqNet accelerator which is generated using High-Level Synthesis (HLS). ZynqNet implements a 4-layer CNN trained on the SAT-6 dataset for aerial image classification. The goal is to evaluate the impact of several fault-tolerance strategies applied at different levels of architectural granularity based on Triple Modular Redundancy (TMR), including Modular TMR (MTMR), Coarse-Grained TMR (CGTMR), and Distributed TMR (DTMR), targeting bit flips in the configuration memory (CRAM) of the Field-Programmable Gate Array (FPGA). Additionally, memory scrubbing was implemented to correct and prevent the accumulation of CRAM faults over time, while error detection and correction codes (EDAC) were employed to protect volatile data stored in caches. The evaluation was validated through both fast, low-cost emulated fault injection and real heavy-ion irradiation experiments. Results show that the combination of DTMR, EDAC, and CRAM scrubbing at a reliability above 90% improves the expected mission image by 4.8× in emulation and 6.31× in irradiation.