Heavy-Ion Radiation Fault Analysis of URSA: A Reconfigurable Systolic Array for CNN Acceleration in SRAM-Based APSoC

Convolutional Neural Networks (CNNs) are increasingly used for on-board image classification in satellites and aerial vehicles, but their deployment on SRAM-based FPGAs and All-Programmable System-on-Chip (APSoC) is limited by radiation-induced faults. This work introduces URSA, a reconfigurable Systolic Array (SA) accelerator for CNN inference implemented on AMD Xilinx Zynq-7000 devices. URSA allows design-time configurability of array geometry and memory organization, enabling the systematic experimental evaluation of how these architectural choices interact with fault-tolerance techniques to determine system-level reliability. A heavy-ion irradiation campaign at the SAFIIRA facility evaluated multiple URSA variants against naive and Arm-based baselines, considering Triple Modular Redundancy (TMR), configuration scrubbing, and Error Detection and Correction (EDAC). Results show that URSA consistently outperforms baselines, that combining TMR and scrubbing provides the most effective resilience improvements, and that OCM-based configurations outperform BRAM-based ones due to reduced programmable logic exposure. From these results, four architectural design guidelines are derived, providing quantified, experimentally validated recommendations for systolic-array CNN accelerators in radiation-prone environments.