A Charge Pump-Based Switched-Capacitor LDO With a Coarse-Fine VCO Achieving Sub-15-ns Settling Time from 0.45-V to 1-V Input Range

This paper presents a charge pump-based switched capacitor low-dropout (CPSC-LDO) regulator with a coarse-fine voltage-controlled oscillator (VCOCF) for area-efficient and high speed system-on-a-chip (SoC) fields. The CPSC-LDO consists of a PMOS pass transistor (MPT), a coupling capacitor (CC), a time quantizer, a switched-capacitor (SC) controller, and coarse-fine SC converters. For a small area, the proposed regulator utilizes a charge pump in the coarse SC converters to decrease the size of coarse capacitors by about half. To improve transient responses, a direct clock and the proposed VCOCF are employed in the time quantizer, where the direct clock also reduces the number of the coarse SC converters from four to two. Moreover, to mitigate a long recovery time (Trecover) to a reference voltage (VREF) inherent in the time quantizer, a coarse lock logic is devised. Therefore, the proposed CPSC-LDO fabricated in a 28-nm CMOS process achieves an active area of 0.025 mm2and a settling time (Tsettle) of sub-15 ns across all input voltage (VIN) ranges from 0.45 V to 1 V. It also achieves a peak current efficiency of 99.97% and a figure of merit (FoM) of 9.4 fs at VIN = 0.45 V.