Dynamic Voltage Imbalance Mitigation during Soft-Switching operation in Series-Connected 10kV SiC MOSFETs and 10kV SiC JBS Diodes for 3L-NPC Converter

This paper presents three design methods for the Dynamic Voltage Balancing (DVB) across series-connected 10kV SiC MOSFETs and 10kV SiC JBS diodes for Medium Voltage (MV) Three-Level (3L) Neutral Point Clamped (NPC) converter for soft-switching. An analytical model is developed by considering the effect of base plate capacitance, parasitic capacitance across load inductor, parasitic bus bar inductance, load inductance and common mode (CM) choke tied between the heat sink and midpoint of the DC link capacitor on the turn-off voltage transition and switching loss across devices. The model has been used for designing the snubber capacitors, snubber resistors, turn-off gate resistance and turn-off timing delay to limit the dynamic voltage mismatch, DC offset voltage and switching losses within the specified limits. The experimental results at 8kV DC bus, 10A load current show that the proposed method ensures DVB across the SiC MOSFETs and JBS diodes with a turn-off voltage mismatch and a DC offset voltage of no more than 39V (1.95%) and 40V (2%), respectively. The 3L-NPC pole with snubber circuits designed by the two methods have achieved an efficiency of over 99.2%.