A Switching Bus Converter Enabling Direct 48-V-to-Point-of-Load Vertical Power Delivery for High-Performance Data Center Processors
Abstract
This article presents a high-density, low-profile switching bus converter for vertical power delivery (SBC-VPD) on next-generation high-performance computing platforms. The proposed design is a hybrid switched-capacitor (SC) voltage regulator module (VRM) that directly steps down a 48 V input to the point-of-load (PoL). It leverages the benefits of the switching bus architecture and a high-order SC network with an increased SC stage conversion ratio. Moreover, it improves upon previous SBC iterations through higher-frequency operation, an assistive resonant charge recovery (RCR) circuit enabling near-zero-voltage-switching (ZVS) operation of high-voltage switches, compact packaging with a layout optimized for VPD, custom vertical coupled inductors, and an improved gate drive design. A 48-V-to-PoL hardware prototype was developed and tested up to 600 A to experimentally validate the proposed design and the efficacy of the RCR circuitry. The prototype, with a total height of 4.7 mm, achieves an areal current density of 0.614 A/mm$^{2}$, meeting stringent VPD constraints of$\leq 5$mm in height and$\geq 0.5$A/mm$^{2}$in current density. For 48 V-to-0.65 V conversion, it delivers a power density of 1392 W/in$^{3}$, a peak system efficiency of 85.3%, and a full-load system efficiency of 77.2%. For 48 V-to-0.8 V conversion, it achieves a power density of 1713 W/in$^{3}$, a peak efficiency of 87.1%, and a full-load system efficiency of 79.5%. Additionally, the RCR circuit yields an experimentally verified system efficiency improvement of approximately 1% through switching loss reduction. This prototype advances the state-of-the-art in 48 V-to-PoL conversion, pushing the boundaries of both academic research and commercial products toward higher efficiency and power density.
Fields of Study & Subjects
Advanced DC-DC Converters
Low-power high-performance VLSI design
Electromagnetic Compatibility and Noise Suppression
Publication details
- Journal / source
- IEEE Transactions on Power Electronics
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Pages
- 1–22
- Publication date
- 1 January 2026