Polymer-Coated Insulation Enhancement on Chip Neighborhood in 10 kV SiC MOSFET Power Modules

High-voltage silicon carbide (SiC) MOSFETs (≥10 kV) offer significant advantages in power density and switching performance but face critical insulation challenges in packaging. This work identifies a previously overlooked electric field concentration region — the chip neighborhood, particularly beneath bonding wires. To address this, it is proposed that a polymer coating high dielectric strength, applied to shield critical areas. Simulation results show that a coating thickness of 20 μm can reduce the maximum electric field strength in the silicon-gel by 25.9% in the case without bonding wires, and by 37.7% in the case with a bonding wire height of 1000 μm. Partial discharge experiments demonstrate that the coating can prevent the chip from experiencing partial discharge under at least 10kV excitation. The module encapsulated by the coated chip has passed the high-speed double pulse test at 7kV and the 168-hour high temperature reverse bias (HTRB) test. These results validate the solution's efficacy for high-voltage SiC device applications.