Variable Reference Voltage PWM for Five-Level Stacked Multicell Converter With Capacitor Voltage Balancing and Reduced Common-Mode Voltage

Carrier-based modulation strategies with natural capacitor voltage balancing characteristics are widely employed in five-level stacked multicell (SM) converters, owing to their straightforward implementation and reduced capacitor requirements. However, active voltage balancing of DC-link capacitors usually requires zero-sequence voltage (ZSV) or harmonic voltage injection, which introduces significant common-mode voltage (CMV) and degrades system performance. To overcome this limitation, this paper proposes a variable reference voltage pulse-width modulation (VRV-PWM) strategy. The proposed method leverages a novel neutral-point (NP) current expression, derived from the SM converter's switching states, to regulate the NP current via duty cycle adjustment, thereby operating without ZSV or harmonic injection. Consequently, this approach maintains an average phase voltage free of low-frequency components while achieving zero average CMV, which significantly suppresses the instantaneous CMV and enhances the output phase voltage performance. An optimal NP current regulation scheme is further derived to achieve independent and decoupled voltage control across all capacitors. Theoretical analysis shows that the proposed strategy complements traditional methods in NP voltage balancing, effectively overcoming their drawback in suppressing low-frequency voltage fluctuations under low power factor conditions. Experimental results confirm the effectiveness of the proposed VRV-PWM, demonstrating its superior performance in CMV reduction and output phase voltage harmonic quality.