An SVPWM Method of Three-Level SNPC Inverter to Achieve ZVS of Inverter Stage Devices and Reduce CM Ripple Based on Zero Vector Transitions

The three-phase three-level (3-L) sparse neutral point clamped (SNPC) inverter features a reduced number of power semiconductor devices, compared to the classical 3-L NPC and T-type inverters, representing a promising alternative for industrial motor drives and electric vehicle traction systems. However, the switching losses of the 2-L inverter stage increase significantly under non-unity power factor condition when applying conventional sequences, resulting in reduced efficiency. To address this issue, a novel space vector pulse width modulation (SVPWM) method based on zero vector transitions is proposed in this article. The proposed sequence achieves zero voltage switching (ZVS) of the 2-L inverter stage devices. Thus, the switching losses of the 2-L inverter stage can be theoretically eliminated. Furthermore, the dwell-time calculation of the vectors is reconsidered, and an adjusting parameter is introduced, which influences the differential-mode (DM) and common-mode (CM) voltage-time area ripples. Finally, experimental validation on a 1.5-kVA hardware prototype demonstrates that the proposed method achieves higher efficiency over a wide power factor range, with a 0.3% increase at inductive load (PF = 0.7) and a 0.35% increase at capacitive load (PF = 0.65) compared with the conventional low-switching loss modulation method. Meanwhile, the proposed method generates lower CM voltage-time area ripple over a wide modulation index range, which is further verified by CM current measurements.