Failure Behavioral Process and Mechanism of SiC MOSFETs Under Dynamic Reverse Bias

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) increasingly operate under high voltage and fast switching conditions, making dynamic reverse bias (DRB) testing essential for evaluating their reliability. This letter presents a failure behavioral process and mechanism of 1.2 kV SiC MOSFETs under DRB stress. The observed failure mode was gate oxide breakdown, attributed to gate crosstalk caused by dVDS/dt-induced displacement current during rapid VDS transitions. This study reveals the dynamic evolution process of carriers and electric field at the SiC/SiO2 interface under DRB timing sequence. The leakage path induced by DRB stress was characterized by IGSS-, IDSS, and failure analysis. TCAD simulations revealed that the electric field gradually accumulated during DRB stress, with the highest field appearing at the edge of the gate oxide. These findings provide crucial insights into DRB induced failure and offer a practical framework for the reliability assessment of SiC MOSFETs.