Mechanisms of Chip-Scale Thermal Concentration in SiC MOSFETs During Avalanche Breakdown

Avalanche failures in Silicon Carbide (SiC) MOSFETs often localize to small burned areas, revealing significant thermal concentration that limits device ruggedness. This work systematically investigates the underlying physical mechanisms, identifying three primary contributors: non-uniform heat generation and dissipation governed by chip layout and package design; cell-level current crowding driven by chip-scale temperature gradients; and impact ionization anisotropy inherent to the 4H-SiC material. Finite-element simulations, spanning from the chip to the cell scale, clarify these coupled electro-thermal processes. The mechanisms are experimentally validated using specially fabricated SiC MOSFETs through unclamped inductive switching (UIS) tests, decapsulation (DECAP) analysis, and statistical correlation of failure locations with single-pulse avalanche energy (EAS). The results conclusively confirm that mitigating thermal concentration via the proposed framework enhances avalanche ruggedness, providing device designers with a systematic approach to alleviate design trade-offs and a practical guideline for rapid failure analysis.