High Performance 3-D Stacked Packaging of SiC Power Module Enabled by Direct Plated Copper Ceramic Interposer

Aiming to solve high parasitic inductance, uneven thermal stress, and excessive junction temperature of power module, a novel 3D stacked packaging architecture incorporating a direct plated copper (DPC) ceramic interposer has been proposed. Attributed to high thermal conductivity and suitable CTE of DPC interposer, The DPC-based 3D stacked SiC power module demonstrates an internal interconnection parasitic inductance as low as 4.74 nH, a maximum thermal stress reduction of 28.14 MPa, and a junction temperature decrease of 49.03°C compared to conventional PCB-based 3D stacked packaging. Moreover, the maximum stress difference between high-side and low-side SiC MOSFET chips decreases by 79.5%, the stress imbalance between SiC diode chips is improved by 84.3%, while the junction temperature difference is minimized to only 7.42°C. The fabricated 3D stacked SiC power module also exhibits robust static and dynamic performances, confirming its suitability for high power density and high frequency applications.