A Capacitorless LDO With Adaptive Zero Compensation and Bulk Negative Capacitance for Whole-Load Stability and High PSRR

The stability of a capacitor-less low-dropout regulator (LDO) is critical to the performance of the system on chips (SoCs). Because the dominant pole is typically load dependent, there is a stability challenge across the whole load current range, particularly at light-load current in capacitor-less LDOs design. To address this, a proposed capacitor-less LDO, which combines an adaptive zero compensation (AZC) methodology with a flipped voltage follower (FVF) loop, alleviates the stability issue and achieves fast transient response without extra quiescent current. Moreover, a negative capacitance circuit (NCC) is proposed to suppress the power supply noise coupling through the parasitic capacitance of the output power transistor and enhance the power supply rejection ratio (PSRR). The proposed capacitor-less LDO is implemented in a 180 nm standard CMOS process and occupies an active chip area of 0.0261 mm². The proposed AZC achieves a phase margin exceeding 45 degrees with the whole load-current from zero to 40 mA maximum load current. With a 36 μA minimum quiescent current, the experimental results show that the proposed LDO achieves a 0.5 ns transient response under a current step of 40 mAload with 2 ns edge time and a PSRR greater than-56 dB at 1 MHz. Good loop stability, transient responses and PSRR are achieved with a 0.45 ps and a 2.2 mV figure of merits (FOMs).