Power Supply Induced Jitter: Introduction and Recent Advances

Jitter is a critical concern in modern electronic systems, particularly as semiconductor devices increasingly operate with low supply rails to minimize power consumption. This paper provides a comprehensive review of Power Supply Induced Jitter (PSIJ), which refers to timing variations directly caused by fluctuations in the power supply voltage. It examines the fundamental mechanisms of PSIJ and presents generalized models for predicting jitter. System-level jitter tracking characteristics are analyzed for serial links, memory interfaces, and synchronous logic to explain the resulting jitter spectrum. The paper also summarizes various pre-silicon PSIJ modeling techniques, including time-domain, frequency-domain, slope-based, and delay-based methods. Finally, recent advancements in PSIJ research are discussed.