A Flat-Gain 255–315 GHz Power Amplifier With 15.5 dBm Maximum P$_{\text{sat}}$ and 5.5% $\eta _{c}$ in 130 nm Advanced SiGe BiCMOS Technology

This work presents a two-way J-band power amplifier (PA) with a flat gain response and high saturated output power (P$_\rm{sat}$). The PA is manufactured in an advanced 130 nm BiCMOS technology from IHP with experimental$f_{T}$and$f_{max}$of 470 GHz and 650 GHz, respectively. The PA is designed to achieve state-of-the-art P$_\rm{sat}$and collector efficiency ($\eta _{c}$) across a wide bandwidth while maintaining a flat gain response. The design methodology to achieve these goals is presented. The PA consists of 3-cascaded amplification stages with gain staggered inter-stage matching. The distribution and combining passives also serve as the matching networks for the amplification stages. The fabricated power amplifier was measured demonstrating a maximum collector efficiency of 5.5% at a saturated output power of 15.5 dBm. These results were achieved with a small-signal gain of 20 dB, a flat gain response of$\pm$0.6 dB from 255 GHz to 315 GHz. With 0.16 mm$^\rm{2}$of occupied silicon area, this design is well suited for J-band transmitting arrays for communication and sensing applications.