A First-Settle, First-Convert Scheduling Scheme for Low-Latency AI Inference in Crossbar Arrays

Resistive random access memory (RRAM) crossbar arrays enable analog in-memory computing, promising high parallelism and reduced data transfer for deep neural networks (DNNs) inference. However, when many columns share a single time-multiplexed analog-to-digital converter (ADC), readout latency, dominated by serialized conversion, can become a performance bottleneck. This article presents the First-Settle, First-Convert (FSFC) readout architecture, a readiness-driven ADC scheduling scheme for RRAM-based fully connected neural networks (FCNNs). Conventional crossbar readout relies on global settling, where all bitlines must wait for the slowest column to stabilize before sequential conversion begins. FSFC replaces this schedule with per-column readiness detection and a priority-queue encoder that continuously routes the earliest-settled column to the shared ADC, overlapping bitline settling and conversion without adding extra ADCs or changing the crossbar. Software experiments and SPICE-level circuit simulations in SkyWater 130 nm show that FSFC reduces inference latency by 35%–67% across 1- to 8-bit quantized MNIST FCNNs, with no loss of classification accuracy. A transistor-level implementation of the differentiator, hysteresis comparator, and digital priority-queue encoder incurs about 80 pJ of control energy per matrix-vector multiplication (MVM) for a$30\times 10$array, scaling to approximately 1 nJ per MVM and about 5%–8% tile area overhead for a 128-column tile. Because FSFC shortens ADC active time while introducing only modest peripheral circuitry, it provides a low-cost, drop-in latency improvement for RRAM compute-in-memory (CIM) tiles. The technique is orthogonal to existing ADC pooling, precision-reduction, and analog-cascading schemes, and can be integrated as a readout front-end in future crossbar-based accelerators.