HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC nand Flash Memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2026

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Authors: Yongchao Wang, D. Wei, Dixin Ma, Huqi Xiang, Liyan Qiao
DOI: 10.1109/tvlsi.2026.3656525
Cited by: 0
References: 45

Fields of Study & Subjects

Advanced Data Storage Technologies Error Correcting Code Techniques Low-power high-performance VLSI design

Publication details

Journal / source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume
34
Issue
3
Pages
725–736
Publication date
6 February 2026