RAEnc: A Stall-Less Metadata Compression Framework for Return Address Integrity on High-Performance Embedded Processors

Protecting return address integrity (RAI) on high-performance embedded processors (HPEPs) is more challenging than on traditional microcontroller units (MCUs) or server processors. Isolation-based schemes such as shadow stacks fail against hardware memory threats, while crypto-based schemes remain vulnerable to forgery and replay attacks. To address the challenges of RAI protection in HPEPs, this article presentsRAEnc, a novel crypto-based scheme, which provides comprehensive RAI against both forgery and replay attacks with negligible performance overhead via hardware–software co-design. We first introduce the metadata compression during return address encryption (MCRAE), a cryptographic primitive compressing the call stack’s integrity state into a single, register-resident value using custom RISC-V instructions, thereby eliminating the memory attack surface. We then detail the stall-less encryption/decryption unit (EDU) that is tightly coupled with the processor pipeline. By employing speculative scheduling, a low-latency 128-bit QARMA unit, encryption/decryption cache (EDCache), and multichain parallelism, the EDU eliminates pipeline stalls common in decoupled accelerators. Implemented on the open-source BOOM processor,RAEncincurs a negligible 0.2% performance overhead on embedded and SPEC CPU2017 workloads with modest hardware cost, outperforming existing crypto-based RAI schemes in both security and performance.