A 0.67–5.67-GHz Ring-Based MDLL With 154-fs RMS Jitter and Stochastic Sampling for Spurious Tone Reduction in 5-nm FinFET

A highly digital multiplying delay-locked loop (MDLL) fabricated in TSMC’s 5-nm FinFET technology achieves a wide frequency range of 0.67–5.67-GHz while consuming 6.69mW and occupying 0.0022 mm2of active area. The design employs a ring-oscillator-based digitally controlled oscillator (RO-DCO) that provides 1 MHz frequency granularity and exhibits a −124 dBc/Hz phase-noise level at a 1 MHz offset, yielding an integrated rms jitter of 154 fs (1 kHz–100 MHz). Reference spurious tones caused by static phase offset (SPO) and nonideal clock realignment are mitigated through an in situ stochastic-sampling calibration technique that performs on-chip detection. The proposed correction technique suppresses spurs without compromising jitter or power efficiency, enabling a compact, low-overhead all-digital implementation. The MDLL demonstrates that ring-oscillator-based architectures can simultaneously achieve broad frequency programmability, sub-200-fs jitter, and spur suppression at low power and area cost. These results demonstrate suitability for high-performance clock generation in advanced SoCs and multi-Gb/s applications where analog PLLs face scaling limitations.