A Hardware Attack Secure SRAM: A HAS-16T SRAM Cell Resistant to Side Channel Attacks and Fault-Injection Attacks

This article presents the HAS-16T static random access memory (SRAM) cell, a novel 16-transistor design implemented in 45 nm CMOS technology to achieve robust security against side-channel attacks (SCAs) and fault injection attacks (FIAs). The cell integrates sleep transistors, loop-cut mechanisms, prewrite conditioning, and an inverter feedback loop to mitigate leakage power analysis (LPA), timing analysis attacks (TAAs), and FIAs. A comprehensive security measure, based on Monte Carlo simulations (1000 samples, 1 V,$27~^{\circ } $C), quantifies resistance through histogram overlap and failure probability, yielding a total security matrix (SMTotal) of 98.68%, the highest among evaluated cells (e.g., 6T: 38.37%, EQ-14T: 68.91%). Simulations in the Cadence design environment reveal the HAS-16T’s second-highest static noise margin (SNM), moderate read/write delays, second-lowest write dynamic power, and second-highest leakage power, reflecting a balanced tradeoff for security-critical applications. Compared to conventional and secure SRAM designs, the HAS-16T offers unparalleled protection, making it ideal for cryptographic and embedded systems. Future work includes area optimization and scalability to advanced process nodes.