Back-Gate Voltage Scaling for Error Generation in LPPN on 22-nm FD-SOI Technology

The increasing deployment of digital communications in modern society has heightened the need for security and privacy, particularly within the Internet-of-Things (IoT) domain, where cost-effective implementations remain a challenge. Post-quantum cryptography (PQC) schemes based on hard learning problems, such as learning with errors (LWEs) and learning parity with noise (LPN), have gained significant attention due to their robustness against quantum attacks. A key challenge in these cryptographic schemes is the generation of error distributions, which must maintain secrecy and adhere to specific statistical properties. Traditional approaches rely on complex two-phase sampling chains, making hardware implementations both resource-intensive and vulnerable to physical attacks. To address these challenges, inexact or approximate computing has been explored as a means of generating errors. The learning parity with physical noise (LPPN) scheme was introduced as an alternative, leveraging controllable computational inaccuracies instead of explicit error sampling. Initially demonstrated using frequency–voltage Over-Scaling techniques on a 65-nm technology, its viability on advanced semiconductor nodes remains uncertain. In this work, we implement the LPPN technique on a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology, assessing the limitations of conventional voltage–frequency Over-Scaling. Furthermore, we propose the use of back-gate voltage scaling, a unique capability of FD-SOI, to enhance error controllability. Experimental results from both simulations and on-chip measurements demonstrate that back-gate voltage scaling improves the precision of error generation, reducing the sensitivity factor of the error probability by up to four times compared to conventional methods.