PipeCHX: A High-Bandwidth-Low-Latency Hybrid CXL Memory Controller

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2026

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Authors: Xingyu Chen, Fei Wang, Yuan Tian, Shan Zhao, Xiaoyong Xue, Xiaoyang Zeng
DOI: 10.1109/tvlsi.2026.3658749
Cited by: 0
References: 18

Fields of Study & Subjects

Interconnection Networks and Systems Parallel Computing and Optimization Techniques Embedded Systems Design Techniques

Publication details

Journal / source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume
34
Issue
4
Pages
1253–1266
Publication date
6 February 2026