On-Chip Warpage Extraction Through Ring Oscillator Delay Testing

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Authors: Min Kim, Seohyun Kim, Youngsoo Shin
Cited by: 0
References: 17

Abstract

Wafer warpage is important and critical issue in 3D-IC as well as 2D-IC. Accurate warpage extraction is necessary to screen out wafers with excessive bending before they proceed to subsequent fabrication steps. The conventional method relies on optical measurement, which can be applied only to a few sample wafers and is not practical for full-wafer inspection in high-volume manufacturing. We propose an on-chip warpage extraction technique that leverages delay variation in ring oscillators (ROs) between prebond and postbond test. A key is to derive the mobility change of nMOS and pMOS transistors from RO delay change. The mobility change is subsequently converted into mechanical stress, which becomes a basis of constructing wafer surface map. Experimental results demonstrate that the proposed method extracts wafer warpage with an accuracy of 94% compared to actual measurement.

Fields of Study & Subjects

VLSI and Analog Circuit Testing 3D IC and TSV technologies Physical Unclonable Functions (PUFs) and Hardware Security

Publication details

Journal / source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume
34
Issue
4
Pages
1383–1387
Publication date
9 February 2026
Language
EN