A Cryogenic 2T GC-eDRAM With an Inverter-Based Readout Scheme and an 80 ms Retention Time

This article presents a novel sensing scheme for a 2T gain-cell embedded dynamic random access memory (GC-eDRAM) optimized for cryogenic temperatures. The proposed design integrates a highly accurate sense amplifier (SA) with a$\pm 3\sigma $sensitivity of 11.16 mV and an internally generated, adjustable reference voltage (VREF) with 9.5 mV step resolution. Additionally, an on-chip ring-oscillator-based design-for-test (RO-DFT) mechanism is introduced to determine the optimal VREF postfabrication, improving readout reliability while adapting to process variations. Simulation results, based on a 65nm CMOS process calibrated for 77 K operation, demonstrate a significant extension of the data retention time (DRT) to 80 ms, reducing refresh cycle frequency and lowering power consumption—critical for cryogenic applications such as infrared imaging. The proposed architecture provides a power-efficient, high-density embedded memory solution for low-temperature computing environments.