A Hardware-Efficient QR Algorithm and Its VLSI Architecture for Eigenvalue Decomposition of Symmetric Matrices

This article proposes a novel hardware-efficient QR algorithm and its VLSI architecture to compute the eigenvalue decomposition (EVD) of symmetric matrices. By replacing the computationally expensive matrix multiplication with matrix transposition, the proposed architecture achieves a significant reduction in latency as well as area compared to the conventional QR architecture. We prove the convergence of the proposed algorithm through mathematical analysis and study its convergence rate through numerical simulations. We implemented both conventional and proposed QR architectures on both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) platforms. Implementation results on the ZCU104 Ultrascale+ FPGA demonstrate a 51% reduction in computation time and a 50% decrease in DSP usage with the proposed algorithm. Furthermore, ASIC synthesis results also demonstrate a significant reduction in computation time compared to the conventional algorithm.