Efficient 3-D Convolutional Neural Network Model and VLSI Architecture for Low-Latency and Low-Complexity Processing

Three-dimensional convolutional neural networks (3D-CNNs) have shown remarkable performance in applications such as point cloud labeling, semantic segmentation, and human action recognition (HAR). However, conventional 3D-CNN models, such as C3D, suffer from high computational and storage demands, incurring significant challenges for hardware acceleration. This article presents an efficient 3D-CNN framework based on 3-D depthwise separable convolution (3DDSC), which significantly reduces the number of parameters and computational complexity. Furthermore, a novel pooling-ahead (PA) technique is proposed to minimize memory access overhead. Based on the proposed 3D-CNN framework, a low-latency and low-complexity VLSI architecture is designed. The proposed design is implemented using the TSMC 40-nm technology and validated on a field-programmable gate array (FPGA) platform. The experimental results show that the FPGA implementation achieves a$6\times $reduction in hardware resource utilization and a$1.7\times $improvement in latency compared to state-of-the-art designs. Moreover, the application-specific integrated circuit (ASIC) implementation attains$1.86\times $lower complexity and$1.1\times $faster latency, further demonstrating the efficiency and scalability of the proposed architecture.