A 28-nm 9-kb SRAM Computing-in-Memory Macro With Segmented Charge Sharing for Multimode MAC Operations

Computing-in-memory (CIM) is a novel approach to solve the von Neumann bottleneck and improve energy efficiency and throughput. This article presents an SRAM-CIM macro based on segmented charge sharing to support multimode multiply-and-accumulate (MAC) operations, including binary weight network (BWN) MAC, ternary weight network (TWN) MAC, and multibit MAC operations. Signed 9-bit input MAC operations can be supported in BWN and TWN networks through multiple cycles. The multibit MAC operations are realized by the cooperation of two cell structures, which eliminates the need to convert negative numbers into complements and reduces the area and power consumption of the chip. Additionally, the proposed segmented charge-sharing scheme increases the speed of accumulation and improves the overall energy efficiency of the chip. The proposed 9-kb macro is implemented in 28-nm CMOS technology with an energy efficiency of 30.74 TOPS/W and an area efficiency of 1.15 TOPS/mm2in multibit MAC mode. At the system level, a ResNet-based model achieves an accuracy of 94.59% on the CIFAR-10 dataset and 74.64% on the CIFAR-100 dataset, demonstrating the effectiveness of the proposed CIM architecture for practical neural network inference. Compared to prior designs, it not only supports additional computing modes but also demonstrates notable improvements in both energy and area efficiency.