A High-Performance ML-KEM Architecture With Task-Level Parallelism

As the standardization of postquantum cryptography progresses, module-lattice-based key-encapsulation mechanism (ML-KEM), the standardized successor to CRYSTALS-Kyber, has become a primary target for hardware deployment. Owing to the tight interactions among ML-KEM compute tasks, achieving end-to-end high performance remains challenging. To address this problem, the proposed task-level parallelism (TLP)-centric system scheduler organizes a highly parallel task flow for ML-KEM, enabling conflict-free overlap among major tasks and substantially reducing the overall cycle count. Furthermore, by codesigning a MUX-steered dual-RAM 2-in/2-out access mechanism and a parallel polynomial compute unit, the memory system and compute fabric jointly sustain this high-parallelism task flow, resulting in a high-performance ML-KEM hardware architecture. Implemented on a Xilinx Artix-7 FPGA at 210 MHz, the proposed architecture supports all three ML-KEM security levels, uses 13.8 K LUTs, 9.6 K FFs, and 3.66 K slices, and completes in 18.9/28.7/$41.8~\mu $s for ML-KEM-512/768/1024, respectively. Compared with the latest designs, the proposed architecture achieves46%–47%shorter runtime,while simultaneously maintaining balanced resource usage and improving area-time product by 21%–23%.