A Fast-Locking Phase-Locked Loop With Joint Phase and Frequency Compensation Technique
Abstract
A fast-locking phase-locked loop (PLL) with a joint phase and frequency compensation technique is presented. With the proposed maximum phase error detector (MPED), the accumulated phase error can be well compensated right after frequency acquisition to improve the settling time of the PLL. The proposed PLL operating at a 0.9-V supply power was fabricated using a 28-nm CMOS process. The total settling time can be improved by 78% with a 200-ppm settling accuracy. The output frequency of the PLL is operated at 10GHz with a power consumption of 2.76mW.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Numerical Methods and Algorithms
Iterative Learning Control Systems
Publication details
- Journal / source
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 34
- Issue
- 7
- Pages
- 2301–2305
- Publication date
- 22 April 2026