Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks

This article proposes a probability-driven intercolumn error cancellation mechanism for approximate multiplier design, enabling an improved tradeoff between computational accuracy and hardware efficiency. By statistically characterizing the error behavior of approximate compressors and coordinating positive and negative error units, effective column-level error cancellation is achieved. Asubarray truncation strategy is further integrated into a recursive multiplier architecture to reduce partial product generation and accumulation overhead. Multiple approximate multipliers with different accuracy levels are implemented and synthesized in a 28-nm CMOS process. Compared with an exact$8{\,}\times{\,} 8$multiplier, the high-accuracy ECM8-1 achieves near-lossless accuracy while reducing the power–area–delay product (PADP) by 35.6%, whereas the low-power ECM-TT22 achieves a reduction of up to 99.6%. In image processing applications, the high-accuracy and low-power designs achieve 99.8% and above 85.4% Structural Similarity Index (SSIM) in blurring, and 99.6% and 84.9% SSIM in edge detection, respectively. In quantized deep neural networks (DNNs) inference workloads, ECM8 incurs less than 0.3% accuracy loss on CIFAR-10, while ECM-O and ECM-T maintain near-exact performance on MNIST, demonstrating robustness across different precision levels and suitability for hardware-efficient DNN acceleration.