MoS 2 -Enhanced Antisymmetric 2T2R Logic Unit for One-Step Write/Compute In-Memory XNOR in BNN Accelerators

The rise of artificial intelligence (AI) and growing energy constraints have intensified the need for efficient, low-power hardware. Thexnorlogic, a cornerstone of low-precision neural network inference, is especially critical to optimize for energy efficiency. Conventional CMOS-based in-memoryxnorunits, however, face key limitations, including low integration density, readout interference, and multistep write protocols. To address these challenges, we present a MoS2transistor-enhanced antisymmetric 2T2R in-memoryxnorlogic unit, enabling both write and compute operations to be finished within a single step, achieving the theoretical minimum for in-memory logic primitives. Beyond logic-level optimization, the incorporation of MoS2transistors facilitates monolithic 3-D integration and lowers static power consumption relative to standard CMOS devices. At the system level, we extend the analog majority architecture to BNN inference, including the weight mapping strategy, and discuss the system-level advantages and quantization errors introduced by this approach.