Design and Performance Analysis of Confidence Selected Phase Detector and Stochastic Delay Loop

A confidence selected phase detector is proposed for digital carrier recovery (CR) loops. By dynamically selecting high-confidence symbols according to instantaneous signal-to-noise ratio (SNR) for phase estimation, the algorithm reduces phase-jitter variance at low SNR and extends the workable region of CR loops in high-order modulation scenarios. Furthermore, the delay induced by symbol discarding is modeled as a stochastic delay system, yielding closed-form expressions for loop stability constraint, equivalent noise transfer, and convergent condition. Based on these results, we propose a global design criterion by jointly optimizes the selection threshold and loop filter parameters. Both theoretical derivations and simulation results show that the proposed algorithm and optimization strategy can lower the 64-quadrature amplitude modulation (64-QAM) stabilizing threshold by over 8 dB and achieve SNR gain exceeding 0.4 dB.