Resistivity Scaling of Topological CoSi Wires to Sub-10 nm for Post-Cu Interconnects

2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2026

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Authors: Guy Cohen, Franco Stellari, Peter Kerns, Leonidas Ocola, John Bruley, Lynne Gignac, Vesna Stanic, C. Lavoie, Nathan Marchack, Joshua T. Smith, Vijay Narayanan, Ching-Tzu Chen
DOI: 10.1109/vlsitechnologyandcir65830.2026.11577451
Cited by: 1
References: 14

Fields of Study & Subjects

Semiconductor materials and interfaces Copper Interconnects and Reliability Molecular Junctions and Nanostructures

Publication details

Journal / source
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Publisher
IEEE
Pages
1–3
Publication date
14 June 2026