Wafer topography impact on focus and defectivity with enhanced method for EUV focus metrology

To achieve finer feature sizes and enhanced imaging resolution, semiconductor lithography continuously pursues shorter exposure wavelengths and increased numerical aperture (NA). At the same time, the depth of focus (DoF) inevitably decreases. Simulations and initial experiments show that the introduction of high-NA extreme ultraviolet (EUV) lithography will lead to 2.5–3X DoF reduction compared with low-NA EUV. With the introduction of high-NA EUV, it is thus expected that focus control will become increasingly critical for achieving the desired pattern fidelity. We describe the results of our scanning electron microscope–based focus metrology method. We describe optimization of our methodology as well as its sensitivity to data collection parameters. Next, we explore the effects of wafer topography in printing results for a low-NA EUV exposure of a 32-nm minimum pitch logic pattern. We use programmed topography to mimic that of a full-loop logic device. Multiple programmed heights are evaluated and densely placed metrology structures are used for focus metrology. Finally, we show how the presence of topography reduces pattern fidelity and introduces defects.