Process control case-studies for high-volume manufacturing of silicon photonics for co-packaged optics applications

Silicon photonics (SiPh) have gained renewed attention due to applications like co-packaged optics (CPO) for AI datacenters. As photonic integrated circuits (PIC) move toward high-volume manufacturing, focus is shifting to performance, reliability and wafer-scale manufacturability. The performance of components such as micro-ring modulators (MRM) and SOI waveguides depends critically on factors such as epi silicon thickness, etch depth, width, sidewall angle, line edge roughness, refractive index variation, and defectivity. This work examines how inline wafer-scale manufacturing process variations affect PIC performance, in particular energy consumption, highlighting implications for metrology, inspection and process control. Power consumption is a key limiter for AI data center growth.