Advanced 2.5D co-packaged optical solutions for high-efficiency AI workloads and cloud computing: delivering 6.4 Tb/s per port, towards 204Tb/s switch-ASICS

This paper focuses on the packaging aspects of a high-speed, low-power, highly parallelized silicon photonics optical transceiver engine, which is configured to deliver 6.4 Tb/s per port for data center and AI training cluster applications developed within the ADOPTION HEU-funded project. The packaging strategy employs silicon interposers, onto which the PIC will be flip-chip assembled alongside an eight-channel driver and eight transimpedance amplifier (TIA) electronic integrated circuits (EICs). Each PIC, which is fabricated at IMEC, includes 16 transmitter and receiver channels, designed to support 112 Gb/s per channel, enabling a total of 6.4 Tb/s per port operation. Within this project, the modulator driver and TIA EICs are being developed using a 22nm FDSOI-CMOS process, with the potential to achieve energy efficiencies below 1pJ/bit at 112Gb/s. By combining 22nm FDSOI CMOS EICs with PICs featuring undercut modulators and filters, we anticipate achieving a Co-packaged optics (CPO) power consumption as low as 2.5pJ/bit.