A routing-centric 3D photonic network-on-chip for in-package AI systems

As artificial intelligence (AI) systems scale toward increasingly dense and heterogeneous in-package integration, data movement between compute tiles, memory, and chiplets has emerged as a dominant contributor to system energy consumption and latency. Conventional electrical interconnects suffer from resistive and capacitive limitations that degrade bandwidth efficiency and require power-intensive repeaters beyond short on-chip distances. Integrated photonic interconnects offer a promising alternative due to their low propagation loss, high bandwidth density, and distance-invariant latency. This work presents a routing-centric three-dimensional photonic network-on-chip architecture tailored for in-package AI systems. The proposed approach emphasizes deterministic Manhattan-style routing implemented across optical redistribution layers, enabling scalable all-to-all connectivity while minimizing waveguide crossings and fabrication complexity. Vertical optical coupling is employed to distribute routing across layers, supporting chiplet-scale and wafer-scale integration without reliance on active optical switching. A comprehensive routing-aware link budget methodology is developed to quantify optical loss, latency, and energy per bit across on-chip, wafer-scale, and package-scale interconnect distances. Analytical modeling shows that the proposed photonic fabric achieves sub-picojoule per bit energy efficiency for wafer-scale links while maintaining sub-nanosecond latency for medium-reach communication. Compared to electrical networks-on-chip, the routing-centric photonic architecture provides significant improvements in energy efficiency and scalability. These results establish structured photonic routing as a practical foundation for next-generation AI accelerators and advanced in-package computing systems.