Cost-effective, high-performance heterogeneous integration for 6.4T and beyond 224Gbps/lane co-packaged-optical engines for AI/ML and data center

Next-Generation Optical Communication: Components, Sub-Systems, and Systems XV 2026

View at publisher
Authors: Jia Qi Wu, Sajay B. N. Gourikutty, Bin He, Rathin Mandal, Boon Long Lau, Ming Chinq Jong, Sandra San, Xin Li, Hongyu Li, Teck Guan Lim, Jason Tsung-Yang Liow, Surya Bhattacharya
DOI: 10.1117/12.3085221
Cited by: 1

Abstract

Heterogeneous integration (HI) is a highly promising approach to integrate photonic and electronic chips to form optical engines (OE) which address the crucial I/O bottleneck in hyperscale Data Centre (DC) switches and AI/ML clusters in high performance computing (HPC). Cost, performance, and manufacturability are key challenges for HI. In this paper we present the design, process-integration, test-results for a novel Fan-out Wafer Level Package (FOWLP) approach to realize cost-effective, volume-manufacturable, high-performance OEs for 1.6T/6.4T and beyond.

Fields of Study & Subjects

Optical Network Technologies Semiconductor Lasers and Optical Devices Advancements in PLL and VCO Technologies

Publication details

Journal / source
Next-Generation Optical Communication: Components, Sub-Systems, and Systems XV
Publisher
SPIE
Pages
17–17
Publication date
4 March 2026