A high-speed column bus readout circuit with negative capacitance for large array CMOS image sensors

This paper proposes a column parallel bias current source structure using a cross-coupled positive feedback network to address the issue of long establishment time of pixel column bus in large array CMOS image sensors. The proposed structure adopts a cross-coupled positive feedback network to achieve a negative capacitance, effectively reducing the column bus parasitic capacitance and improving the establishment speed. The proposed structure is based on the 110 nm 1P4M CIS process for circuit simulation. The simulation results show that under the same static current of 4 μA, the proposed structure reduces the establishment time by 35 % compared to the traditional column bias current source structure, and ensures lower noise of 119 μV. Experimental results have shown that the proposed structure can significantly improve the readout speed of the column bus in large array CMOS image sensors.