Design of a distributed infrared imaging circuit architecture for miniaturized applications

The growing demand for miniaturization, high performance, and high reliability in infrared imaging systems operating in complex environments has exposed the limitations of traditional centralized circuit architectures, which struggle to meet the requirements for high-speed and intelligent image processing due to volume and wiring constraints. This paper presents a distributed circuit architecture for cooled infrared imaging, which optimizes circuit layout and signal transmission to achieve efficient collaboration in spatially constrained conditions. The proposed design divides the imaging circuit into a front-end signal processing circuit and a back-end image processing circuit. The front-end circuit, based on a compact Artix-7 series FPGA, is integrated into the spatially restricted front chamber and is responsible for signal acquisition, amplification, and preliminary processing from the cooled infrared detector. The back-end circuit, utilizing a high-performance Kintex-7 series FPGA, is deployed in the more spacious rear chamber and handles advanced tasks such as image enhancement, noise suppression, and intelligent image processing algorithms. A self-developed communication protocol enables data encoding between the two circuits, allowing transmission of image data, communication commands, and detector control signals over just two differential pairs (a total of six wires). This significantly reduces wiring complexity and the cross-sectional area of cables running between the front and rear chambers. Experimental results demonstrate that the system reliably supports real-time imaging at a resolution of 640 × 512 and a frame rate of 50 Hz, even under conditions of a 10-meter transmission distance and cable ambient temperatures of 150°C. By adopting a distributed design, this study achieves a substantial reduction in the physical size of the front-end processing unit, simplifies system wiring, and maintains robust back-end processing capabilities. This architecture is particularly suitable for infrared imaging applications with strict volume constraints and high-speed processing requirements in systems featuring a front-rear chamber configuration.