Bit-width determination method for FPGA-implemented pulse-compression φ-OTDR

This paper investigates the influence of data bit width on a pulse-compression phase-sensitive optical time-domain reflectometry (φ-OTDR) system and implemented on a field-programmable gate array (FPGA). For the fractional bits, the influence on the noise floor is analyzed, while for the integer bits we mainly focus on the impact on dynamic range. The noise floor affected by fractional bit width includes the noise power spectral density (PSD) and strain resolution, based on the analysis of the raw RBS signal, the final recovered phase, and intermediate data such as the matched filter coefficients and the extracted phase. Simulation results show that when the fractional bit width is reduced from 8 bits to 2 bits, the noise PSD significantly deteriorates by nearly 25 dB, from −74.92 dB (re rad/√Hz) to −50.30 dB (re rad/√Hz). In contrast, increasing the bit width to 16 bits yields only marginal gains, with the noise PSD improving to −75.48 dB (re 𝑟𝑎𝑑/√𝐻𝑧), an increase of 0.56 dB. Also the amplitude of the applied vibration is validated via applying a sinusoidal signal on the involved PZT with fiber wrapped around it to simulate vibration. Simulation results show that the fractional bit width has minimal impact on the quality of the recovered waveform. On the other hand, the influence of the integer bit width on the system dynamic range is investigated by a linearly amplitude-modulated (LAM) signal. The required number of integer bits is determined by the final recovered phase waveform. The system can recover a maximum undistorted phase of approximately 295 rad, corresponding to a dynamic range of 95.6 dB at 10 Hz. This performance requires 10 integer bits, including the sign bit. In summary, these results indicate that, for the pulse-compression φ-OTDR, a fixed-point format with 10 integer bits and 8 fractional bits provides sufficient precision for a 95.6 dB dynamic range and a noise PSD of −74.92 dB (re rad/√Hz). At last, a real-time pulse-compression φ-OTDR is implemented using the FPGA device of XCKU040. We also performed simulations on the Vivado platform to compare FPGA resource cost for fractional bit widths of 16 bits and 8 bits. Adopting 8-bit fractional precision reduces hardware resource consumption by approximately 28.4% in lookup tables (LUTs), 44% in registers, and 3% in DSP slices compared to the 16-bit configuration. The work provides an approach to design the bit width of real-time DAS system based on the performance requirements, especially the noise floor and DR, and enables a practical trade-off between system performance and resource efficiency.