A failure analysis method for AI chips integrating electrical testing and physical optics

Artificial intelligence (AI) chips are key devices supporting the high-quality development of modern artificial intelligence. Various failure modes and mechanisms can occur during their practical use. However, efficient methods and experience for analyzing AI chip failures are still lacking. This paper presents a failure analysis method for AI chips that combines electrical testing and physical optics. The method mainly consists of three steps. Firstly, preliminary inspection through electrical characteristic testing to identify failed chips. Then, the precise localization of the fault position of AI chips is based on physical optics. Finally, mechanistic analysis of the fault location using micro-analysis techniques. Experimental analysis shows that the provided method can effectively detect the specific fault location of the AI chip and identify its failure mechanism, providing a reference for future failure analysis and reliability improvement of AI chips.