Lightweight DSP signal processing architecture for intelligent edge devices

The integration of artificial intelligence in edge computing has driven demand for efficient signal processing models. This paper designs a lightweight DSP signal processing architecture based on a two-stage pipelined multiply-accumulate structure with integrated Butterworth filters, optimizing latency and power consumption over traditional C6000 architectures. The system employs modular STFT and wavelet reconstruction strategies to achieve multi-level parallel processing. Experimental results demonstrate a 39.1% reduction in processing latency, increased throughput to 75.6 Mbps, and 22.3% lower power consumption compared to the traditional architecture, while maintaining stable performance under high-concurrency conditions.