Comprehensive Analytical Modeling and Assessment of Device Physics and Electrostatic Control Mechanisms in Si/SiO2 Junctionless Surrounding-Gate Transistors

Abstract This manuscript outlines an analytical modelling approach for Si/SiO2 Junctionless Surrounding-Gate Field-Effect Transistors (JLSG FETs), addressing electrostatic potential, threshold voltage, and subthreshold swing. Closed-form solutions obtained from the Poisson equation provide concise and computationally efficient computations for device performance metrics. The model explicitly integrates quantum confinement effects influencing carrier distribution in nanoscale channels, in addition to mobility degradation factors that regulate high-field transport constrained in gate-all-around (GAA) systems. These insights culminate in an enhanced drain current of ~10−5 A and a subthreshold slope of < ~60 mV, demonstrating a robust connection with Silvaco TCAD-oriented simulations, ensuring both physical precision and scalability, providing significant design insights for forthcoming low-power, energy-efficient transistors.