Design of novel multi-valued quantum adder circuit

Multi-valued quantum logic presents significant advantages over conventional binary logic, including enhanced information processing capacity and reduced circuit complexity. As a fundamental component of quantum arithmetic units, the efficiency of multi-valued quantum adders is critical to overall system performance. In this paper, a universal construction scheme for multi-valued quantum half adders, full adders, and parallel adders is introduced based on 1-qudit gates and Muthukrishnan–Stroud gates. The proposed design optimizes the carry propagation mechanism from a one-to-one to a one-to-many architecture, thereby reducing the quantum gate count. A key advantage of this approach is the linear scaling of quantum gate size with the system dimension d. The constructed d-valued quantum adder maintains an optimal number of constant inputs and garbage outputs. For dimensions [Formula: see text], the proposed design demonstrates significant improvements in quantum cost and hardware complexity compared to existing methods.