Innovative Post-Cmos Paradigm: In-Plane Nanomagnetic Logic Circuits for Efficient Low Area and Latency

The ongoing reduction of CMOS technology in size is fast reaching the physical and energy efficiency limits, sparking interest in considering post-CMOS logic paradigms. In-plane nanomagnetic logic (iNML) has been selected as one of these promising alternatives as it is nonvolatile, has very low-power dissipation and high density of the device. Nonetheless, the literature on iNML is at the moment confined to simple logic gates and small-scale Boolean circuits, and there have been few attempts at optimized arithmetic architectures that can consider latency and area issues. To fill this gap, this study proposes iNML design framework by systematically assembling and optimizing full adder (FA) and parallel adder circuits to enable efficient arithmetic computation. The proposed framework combines the magnetically coupled signal propagation paths and optimized magnet arrangement strategies, which reduces interconnect overhead and improves signal synchronization. The proposed circuits, in contrast to traditional CMOS and previous iNML implementations, have a balanced trade-off between computation speed and spatial efficiency, confirmed by MagCAD and ToPoliNano simulations. Through experimentation, a small area of iNML FA of 17.918[Formula: see text] [Formula: see text]m 2 and very low latency of 0.185[Formula: see text]ps have been realized, surpassing the current designs of NML designs in the literature. Therefore, this paper is an important advancement to scalable, high-speed and miniaturized arithmetic infrastructure in post-CMOS technology that offers a design framework of magnetically driven logic systems.