Thermal Optimization Strategies for High-Performance Semiconductor (3D) Integrated Circuits

Three-Dimensional Integrated Circuits (3D ICs) have emerged as a promising solution for overcoming interconnect bottlenecks and improving system performance in advanced semiconductor design. However, vertical stacking of multiple active layers introduces severe thermal challenges due to increased power density and limited heat dissipation pathways. This study presents a novel hybrid multi-objective framework, termed the TriMeta Thermal Optimizer, which integrates the Modified Shuffled Frog Leaping Algorithm (MSFLA), Lion Optimization Algorithm (LOA) and Wild Horse Optimization (WHO) to achieve simultaneous optimization of thermal uniformity, wire-length minimization and Through-Silicon Via (TSV) reduction in large-scale 3D ICs. The proposed model incorporates thermal-aware floorplanning, fabrication-level enhancements with SiO 2 –AlN hybrid Interlayer Dielectrics (ILDs) and graphene–Cu nanocomposite Thermal Interface Materials (TIMs) for improved thermal conductivity. Experimental validation using IBM02 and GSRC benchmarks (n100–n600) demonstrated that the TriMeta framework reduced TSV count by 12–14%, wire length by 11–13% and peak temperature variation ([Formula: see text]) by up to 8.9 ∘ C, compared to Simulated Annealing (SA), Particle Swarm Optimization (PSO), Genetic–Ant Colony Optimization (GA–ACO), Multi-Verse Optimization (MVO) and Moth-Flame Optimization (MFO). Additionally, microchannel cooling lowered hotspot temperatures by 15–18% without structural compromise. These findings confirm that TriMeta provides a coherent, scalable and fabrication-compatible solution for next-generation 3D IC thermal optimization, combining spatial efficiency with improved heat dissipation and reliability.